1. Technical Field
The present invention relates generally to row addressing circuits for video displays, and more particularly relates to a single decoder based row addressing circuit that utilizes dedicated latches to enable multiple pre-writes.
2. Related Art
Video display systems have become commonplace in today's electronics marketplace. Laptops, flat screen monitors, televisions, video cameras, digital cameras, personal digital assistants, cell phones, etc., all typically utilize some form of a video display. As the demand for more and more advanced electronic systems continues to grow, the need to provide improved performance for visual displays remains an ongoing challenge.
A typical visual display, such as a liquid crystal display (LCD), is typically configured as an active matrix of pixels that are loaded with pixel data on a row-by-row basis. Each row is selected with a unique address, thereby allowing data to be addressed to individual rows within the display. In advanced display systems, it is advantageous to be able to simultaneously address rows other than the one being written to with picture information. Moreover, in applications such as a single panel, scrolling color application, the ability to address non-contiguous rows is required.
Simultaneous row addressing (i.e., the ability to address multiple rows during a single cycle) is required, for instance, in applications where the process of erasing a previous pixel state needs to be implemented. For example, in high-speed LCD systems, it is necessary to pre-write some blank information to the row of pixels before writing the actual picture because LCD's generally have a relatively long memory period. Often, multiple pre-writes (e.g., two or more) are preferable. Accordingly, systems are required that can address some rows with pre-write data during the same cycle when a row is addressed with picture data.
Prior art systems that provide this functionality typically utilize hardwired logic that allows a row (e.g., row n) and one or more offset rows (e.g., row n-100) to be selected simultaneously. Unfortunately, this requires a very high number of circuits and limits flexibility. Thus, advanced features, such as bi-directional scanning cannot readily be implemented.